Hardware accelerators of various kinds offer a potential for achieving massive performance in applications that can leverage their high degree of parallelism and customization. Examples include graphics processors (GPUs), manycore co-processors, as well as more customizable devices, such as FPGA-based systems, and streaming data-flow architectures.
The research challenge for this topic is to explore new directions for actually realizing this potential. We encourage submissions in all areas related to accelerators: architectures, algorithms, languages, compilers, libraries, runtime systems, coordination of accelerators and CPU, and debugging and profiling tools. Application-related submissions that contribute new insights into fundamental problems or solution approaches in this domain are welcome as well.
Focus
- New accelerator architectures
- Languages, compilers, and runtime environments for accelerator programming
- Programing techniques for clusters of accelerators
- Tools for debugging, profiling, and optimizing programs on accelerators
- Hybrid and heterogeneous computing mixing several, possibly different types of accelerators, and/or CPUs
- Parallel algorithms and applications for accelerators, even beyond what is considered suitable for current accelerator architectures
- Models and benchmarks for accelerators
- Manual optimization and auto-tuning
- Library support for accelerators
Committee
Chair: Bertil Schmidt (Johannes Gutenberg University of Mainz, Germany)
Local chair: Arturo González (University of Valladolid, Spain)
Tobias Grosser (ETH Zürich, Switzerland)
Josef Weidendorfer (Technische Universität München, , Germany)
Rob Van Nieuwpoort (Netherlands eScience Center, The Netherlands)
Seyong Lee (Oak Ridge National Laboratory, USA)
Jorge González-Domínguez (University of A Coruña, Spain)
Deming Chen (University of Illinois, USA)